Multi-port random access memories (RAM) are substantially faster than standard RAM and commonly referred to as video random access memories (VRAM) because of their effectiveness in video systems. In its simplest form, a multi-port memory includes a dynamic random access memory (DRAM), a DRAM controller, at least one serial memory and a serial memory controller. Each serial memory is essentially a long shift register which can receive a block of data from the DRAM and serially shift the data out through a serial data port. Each serial memory can also serially shift data in through the serial port and transfer data to the DRAM.
The DRAM is a dynamic array for storing multiple bit registers in multiple two dimensional planes each having rows and columns. Each bit register is defined by the same row and column addresses in each of the planes. Each serial memory has a bit register row associated with one of each of the planes of the DRAM such that the columns of the DRAM correspond to the bits of the register row.
In general, the DRAM and serial memory can operate either independently or in combination for internal transfers of data. When operating in combination, the serial memory is structured to allow access to one row of the DRAM. Assuming, in a DRAM having 512 column addresses in each row, a serial memory can read or write to addresses 0-511 of one row of the DRAM. This configuration allows for both bi-directional internal transfers of data between the DRAM and the serial memory and independent access to each memory.
The DRAM is comprised of an arrangement of individual memory cells. Each memory cell typically comprises a capacitor capable of holding a charge and an access transistor for accessing the capacitor charge. The charge is referred to as a data bit and can be either a high voltage or a low voltage. Data can be either stored in the memory cells during a write mode, or data may be retrieved from the memory cells during a read mode. The data is transmitted on signal lines, referred to as Digit lines, which are coupled to input/output lines through transistors used as switching devices. For each bit of data stored, its true logic state is available on an I/O line and its complementary logic state is available at on an I/O compliment line. Thus, each memory cell has two digit lines, Digit and Digit complement.
Typically, the memory cells are arranged in an array and each cell has an address identifying its location in the array. The array comprises a configuration of intersecting rows with a memory cell at each intersection. In order to read from, or write to a cell, the particular cell in question must be addressed. The address for the memory cell is represented by input signals to a row decoder and to a column decoder. The row decoder activates a word line in response to the row address. The selected word line activates the access transistors for each of the memory cells in communication with the selected word line. The column decoder selects a Digit line pair in response to the column address. For a read operation the selected word line activates the access transistors for a given row address, and data is latched to the digit line pairs.
As stated, conventional dynamic memories use memory cells fabricated as capacitors in an integrated circuit to store data. That is, a logical "1" is stored as a charge on the capacitor and the capacitor is discharged for a logical "0". The pairs of digit lines are connected to both memory cells and sense amplifiers. These sense amplifiers are utilized to sense small differentials on the digit line pairs and drive the digit lines to full power supply rails for either reading the memory cells or writing thereto. Once the data has been sensed it can be transmitted to a serial memory via the digit line pairs.
In general, to transfer data from a DRAM to a serial memory, such as a serial access memory (SAM), the data stored in the DRAM is sensed as a differential voltage and then the memories are connected using two transfer lines. If the SAM is storing data which is different from the data being transferred from the DRAM, the DRAM must over-write the SAM. This operation is both time consuming and requires a substantial amount of current.
Further, to respond to the demand for integrated dynamic memory circuits having more storage potential, the size of the individual memory cells have been reduced to fit more memory cells into the same integrated circuit die. The sense amplifiers used to sense data stored in the dynamic memory cells have not been reduced sufficiently, however, to allow the sense amplifiers to be single pitched with the memory cells, complex memory array to sense amplifier layouts cannot be avoided, particularly if sense amps are shared for efficiency. As a result of complex layouts, transfer circuitry between the DRAM and the SAM requires that the die area be increased to accommodate pairs of transfer lines. The full efficiency of the reduced memory cell size used in the integrated memory circuit, therefore, cannot be fully exploited. A transfer circuit is needed which can transfer data between a DRAM and a SAM with less operating current and a reduced die area requirement.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a transfer circuit and method for transferring data between a static memory and a dynamic memory using a single transfer line.